R4300.h (17474B)
1 /************************************************************************** 2 * * 3 * Copyright (C) 1995, Silicon Graphics, Inc. * 4 * * 5 * These coded instructions, statements, and computer programs contain * 6 * unpublished proprietary information of Silicon Graphics, Inc., and * 7 * are protected by Federal copyright law. They may not be disclosed * 8 * to third parties or copied or duplicated in any form, in whole or * 9 * in part, without the prior written consent of Silicon Graphics, Inc. * 10 * * 11 **************************************************************************/ 12 13 /************************************************************************** 14 * 15 * $Revision: 1.13 $ 16 * $Date: 1997/02/11 08:15:34 $ 17 * $Source: /disk6/Master/cvsmdev2/PR/include/R4300.h,v $ 18 * 19 **************************************************************************/ 20 21 #ifndef __R4300_H__ 22 #define __R4300_H__ 23 24 #include <PR/ultratypes.h> 25 26 /* 27 * Segment base addresses and sizes 28 */ 29 #define KUBASE 0 30 #define KUSIZE 0x80000000 31 #define K0BASE 0x80000000 32 #define K0SIZE 0x20000000 33 #define K1BASE 0xA0000000 34 #define K1SIZE 0x20000000 35 #define K2BASE 0xC0000000 36 #define K2SIZE 0x20000000 37 38 /* 39 * Exception vectors 40 */ 41 #define SIZE_EXCVEC 0x80 /* Size of an exc. vec */ 42 #define UT_VEC K0BASE /* utlbmiss vector */ 43 #define R_VEC (K1BASE+0x1fc00000) /* reset vector */ 44 #define XUT_VEC (K0BASE+0x80) /* extended address tlbmiss */ 45 #define ECC_VEC (K0BASE+0x100) /* Ecc exception vector */ 46 #define E_VEC (K0BASE+0x180) /* Gen. exception vector */ 47 48 /* 49 * Address conversion macros 50 */ 51 #ifdef _LANGUAGE_ASSEMBLY 52 53 #define K0_TO_K1(x) ((x)|0xA0000000) /* kseg0 to kseg1 */ 54 #define K1_TO_K0(x) ((x)&0x9FFFFFFF) /* kseg1 to kseg0 */ 55 #define K0_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg0 to physical */ 56 #define K1_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg1 to physical */ 57 #define KDM_TO_PHYS(x) ((x)&0x1FFFFFFF) /* direct mapped to physical */ 58 #define PHYS_TO_K0(x) ((x)|0x80000000) /* physical to kseg0 */ 59 #define PHYS_TO_K1(x) ((x)|0xA0000000) /* physical to kseg1 */ 60 61 #else /* _LANGUAGE_C */ 62 63 #define K0_TO_K1(x) ((u32)(x)|0xA0000000) /* kseg0 to kseg1 */ 64 #define K1_TO_K0(x) ((u32)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ 65 #define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg0 to physical */ 66 #define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg1 to physical */ 67 #define KDM_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* direct mapped to physical */ 68 #define PHYS_TO_K0(x) ((u32)(x)|0x80000000) /* physical to kseg0 */ 69 #define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */ 70 71 #endif /* _LANGUAGE_ASSEMBLY */ 72 73 /* 74 * Address predicates 75 */ 76 #define IS_KSEG0(x) ((u32)(x) >= K0BASE && (u32)(x) < K1BASE) 77 #define IS_KSEG1(x) ((u32)(x) >= K1BASE && (u32)(x) < K2BASE) 78 #define IS_KSEGDM(x) ((u32)(x) >= K0BASE && (u32)(x) < K2BASE) 79 #define IS_KSEG2(x) ((u32)(x) >= K2BASE && (u32)(x) < KPTE_SHDUBASE) 80 #define IS_KPTESEG(x) ((u32)(x) >= KPTE_SHDUBASE) 81 #define IS_KUSEG(x) ((u32)(x) < K0BASE) 82 83 /* 84 * TLB size constants 85 */ 86 87 #define NTLBENTRIES 31 /* entry 31 is reserved by rdb */ 88 89 #define TLBHI_VPN2MASK 0xffffe000 90 #define TLBHI_VPN2SHIFT 13 91 #define TLBHI_PIDMASK 0xff 92 #define TLBHI_PIDSHIFT 0 93 #define TLBHI_NPID 255 /* 255 to fit in 8 bits */ 94 95 #define TLBLO_PFNMASK 0x3fffffc0 96 #define TLBLO_PFNSHIFT 6 97 #define TLBLO_CACHMASK 0x38 /* cache coherency algorithm */ 98 #define TLBLO_CACHSHIFT 3 99 #define TLBLO_UNCACHED 0x10 /* not cached */ 100 #define TLBLO_NONCOHRNT 0x18 /* Cacheable non-coherent */ 101 #define TLBLO_EXLWR 0x28 /* Exclusive write */ 102 #define TLBLO_D 0x4 /* writeable */ 103 #define TLBLO_V 0x2 /* valid bit */ 104 #define TLBLO_G 0x1 /* global access bit */ 105 106 #define TLBINX_PROBE 0x80000000 107 #define TLBINX_INXMASK 0x3f 108 #define TLBINX_INXSHIFT 0 109 110 #define TLBRAND_RANDMASK 0x3f 111 #define TLBRAND_RANDSHIFT 0 112 113 #define TLBWIRED_WIREDMASK 0x3f 114 115 #define TLBCTXT_BASEMASK 0xff800000 116 #define TLBCTXT_BASESHIFT 23 117 #define TLBCTXT_BASEBITS 9 118 119 #define TLBCTXT_VPNMASK 0x7ffff0 120 #define TLBCTXT_VPNSHIFT 4 121 122 #define TLBPGMASK_4K 0x0 123 #define TLBPGMASK_16K 0x6000 124 #define TLBPGMASK_64K 0x1e000 125 126 /* 127 * Status register 128 */ 129 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ 130 131 #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ 132 #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ 133 #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ 134 #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ 135 #define SR_RP 0x08000000 /* Reduced power (quarter speed) */ 136 #define SR_FR 0x04000000 /* MIPS III FP register mode */ 137 #define SR_RE 0x02000000 /* Reverse endian */ 138 #define SR_ITS 0x01000000 /* Instruction trace support */ 139 #define SR_BEV 0x00400000 /* Use boot exception vectors */ 140 #define SR_TS 0x00200000 /* TLB shutdown */ 141 #define SR_SR 0x00100000 /* Soft reset occured */ 142 #define SR_CH 0x00040000 /* Cache hit for last 'cache' op */ 143 #define SR_CE 0x00020000 /* Create ECC */ 144 #define SR_DE 0x00010000 /* ECC of parity does not cause error */ 145 146 /* 147 * Interrupt enable bits 148 * (NOTE: bits set to 1 enable the corresponding level interrupt) 149 */ 150 #define SR_IMASK 0x0000ff00 /* Interrupt mask */ 151 #define SR_IMASK8 0x00000000 /* mask level 8 */ 152 #define SR_IMASK7 0x00008000 /* mask level 7 */ 153 #define SR_IMASK6 0x0000c000 /* mask level 6 */ 154 #define SR_IMASK5 0x0000e000 /* mask level 5 */ 155 #define SR_IMASK4 0x0000f000 /* mask level 4 */ 156 #define SR_IMASK3 0x0000f800 /* mask level 3 */ 157 #define SR_IMASK2 0x0000fc00 /* mask level 2 */ 158 #define SR_IMASK1 0x0000fe00 /* mask level 1 */ 159 #define SR_IMASK0 0x0000ff00 /* mask level 0 */ 160 161 #define SR_IBIT8 0x00008000 /* bit level 8 */ 162 #define SR_IBIT7 0x00004000 /* bit level 7 */ 163 #define SR_IBIT6 0x00002000 /* bit level 6 */ 164 #define SR_IBIT5 0x00001000 /* bit level 5 */ 165 #define SR_IBIT4 0x00000800 /* bit level 4 */ 166 #define SR_IBIT3 0x00000400 /* bit level 3 */ 167 #define SR_IBIT2 0x00000200 /* bit level 2 */ 168 #define SR_IBIT1 0x00000100 /* bit level 1 */ 169 170 #define SR_IMASKSHIFT 8 171 172 #define SR_KX 0x00000080 /* extended-addr TLB vec in kernel */ 173 #define SR_SX 0x00000040 /* xtended-addr TLB vec supervisor */ 174 #define SR_UX 0x00000020 /* xtended-addr TLB vec in user mode */ 175 #define SR_KSU_MASK 0x00000018 /* mode mask */ 176 #define SR_KSU_USR 0x00000010 /* user mode */ 177 #define SR_KSU_SUP 0x00000008 /* supervisor mode */ 178 #define SR_KSU_KER 0x00000000 /* kernel mode */ 179 #define SR_ERL 0x00000004 /* Error level, 1=>cache error */ 180 #define SR_EXL 0x00000002 /* Exception level, 1=>exception */ 181 #define SR_IE 0x00000001 /* interrupt enable, 1=>enable */ 182 183 /* 184 * Cause Register 185 */ 186 #define CAUSE_BD 0x80000000 /* Branch delay slot */ 187 #define CAUSE_CEMASK 0x30000000 /* coprocessor error */ 188 #define CAUSE_CESHIFT 28 189 190 /* Interrupt pending bits */ 191 #define CAUSE_IP8 0x00008000 /* External level 8 pending - COMPARE */ 192 #define CAUSE_IP7 0x00004000 /* External level 7 pending - INT4 */ 193 #define CAUSE_IP6 0x00002000 /* External level 6 pending - INT3 */ 194 #define CAUSE_IP5 0x00001000 /* External level 5 pending - INT2 */ 195 #define CAUSE_IP4 0x00000800 /* External level 4 pending - INT1 */ 196 #define CAUSE_IP3 0x00000400 /* External level 3 pending - INT0 */ 197 #define CAUSE_SW2 0x00000200 /* Software level 2 pending */ 198 #define CAUSE_SW1 0x00000100 /* Software level 1 pending */ 199 200 #define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ 201 #define CAUSE_IPSHIFT 8 202 203 #define CAUSE_EXCMASK 0x0000007C /* Cause code bits */ 204 205 #define CAUSE_EXCSHIFT 2 206 207 /* Cause register exception codes */ 208 209 #define EXC_CODE(x) ((x)<<2) 210 211 /* Hardware exception codes */ 212 #define EXC_INT EXC_CODE(0) /* interrupt */ 213 #define EXC_MOD EXC_CODE(1) /* TLB mod */ 214 #define EXC_RMISS EXC_CODE(2) /* Read TLB Miss */ 215 #define EXC_WMISS EXC_CODE(3) /* Write TLB Miss */ 216 #define EXC_RADE EXC_CODE(4) /* Read Address Error */ 217 #define EXC_WADE EXC_CODE(5) /* Write Address Error */ 218 #define EXC_IBE EXC_CODE(6) /* Instruction Bus Error */ 219 #define EXC_DBE EXC_CODE(7) /* Data Bus Error */ 220 #define EXC_SYSCALL EXC_CODE(8) /* SYSCALL */ 221 #define EXC_BREAK EXC_CODE(9) /* BREAKpoint */ 222 #define EXC_II EXC_CODE(10) /* Illegal Instruction */ 223 #define EXC_CPU EXC_CODE(11) /* CoProcessor Unusable */ 224 #define EXC_OV EXC_CODE(12) /* OVerflow */ 225 #define EXC_TRAP EXC_CODE(13) /* Trap exception */ 226 #define EXC_VCEI EXC_CODE(14) /* Virt. Coherency on Inst. fetch */ 227 #define EXC_FPE EXC_CODE(15) /* Floating Point Exception */ 228 #define EXC_WATCH EXC_CODE(23) /* Watchpoint reference */ 229 #define EXC_VCED EXC_CODE(31) /* Virt. Coherency on data read */ 230 231 /* C0_PRID Defines */ 232 #define C0_IMPMASK 0xff00 233 #define C0_IMPSHIFT 8 234 #define C0_REVMASK 0xff 235 #define C0_MAJREVMASK 0xf0 236 #define C0_MAJREVSHIFT 4 237 #define C0_MINREVMASK 0xf 238 239 /* 240 * Coprocessor 0 operations 241 */ 242 #define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */ 243 #define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */ 244 #define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */ 245 #define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */ 246 #define C0_RFE 0x10 /* restore for exception */ 247 248 /* 249 * 'cache' instruction definitions 250 */ 251 252 /* Target cache */ 253 #define CACH_PI 0x0 /* specifies primary inst. cache */ 254 #define CACH_PD 0x1 /* primary data cache */ 255 #define CACH_SI 0x2 /* secondary instruction cache */ 256 #define CACH_SD 0x3 /* secondary data cache */ 257 258 /* Cache operations */ 259 #define C_IINV 0x0 /* index invalidate (inst, 2nd inst) */ 260 #define C_IWBINV 0x0 /* index writeback inval (d, sd) */ 261 #define C_ILT 0x4 /* index load tag (all) */ 262 #define C_IST 0x8 /* index store tag (all) */ 263 #define C_CDX 0xc /* create dirty exclusive (d, sd) */ 264 #define C_HINV 0x10 /* hit invalidate (all) */ 265 #define C_HWBINV 0x14 /* hit writeback inv. (d, sd) */ 266 #define C_FILL 0x14 /* fill (i) */ 267 #define C_HWB 0x18 /* hit writeback (i, d, sd) */ 268 #define C_HSV 0x1c /* hit set virt. (si, sd) */ 269 270 /* 271 * Cache size definitions 272 */ 273 #define ICACHE_SIZE 0x4000 /* 16K */ 274 #define ICACHE_LINESIZE 32 /* 8 words */ 275 #define ICACHE_LINEMASK (ICACHE_LINESIZE-1) 276 277 #define DCACHE_SIZE 0x2000 /* 8K */ 278 #define DCACHE_LINESIZE 16 /* 4 words */ 279 #define DCACHE_LINEMASK (DCACHE_LINESIZE-1) 280 281 /* 282 * C0_CONFIG register definitions 283 */ 284 #define CONFIG_CM 0x80000000 /* 1 == Master-Checker enabled */ 285 #define CONFIG_EC 0x70000000 /* System Clock ratio */ 286 #define CONFIG_EC_1_1 0x6 /* System Clock ratio 1 :1 */ 287 #define CONFIG_EC_3_2 0x7 /* System Clock ratio 1.5 :1 */ 288 #define CONFIG_EC_2_1 0x0 /* System Clock ratio 2 :1 */ 289 #define CONFIG_EC_3_1 0x1 /* System Clock ratio 3 :1 */ 290 #define CONFIG_EP 0x0f000000 /* Transmit Data Pattern */ 291 #define CONFIG_SB 0x00c00000 /* Secondary cache block size */ 292 293 #define CONFIG_SS 0x00200000 /* Split scache: 0 == I&D combined */ 294 #define CONFIG_SW 0x00100000 /* scache port: 0==128, 1==64 */ 295 #define CONFIG_EW 0x000c0000 /* System Port width: 0==64, 1==32 */ 296 #define CONFIG_SC 0x00020000 /* 0 -> 2nd cache present */ 297 #define CONFIG_SM 0x00010000 /* 0 -> Dirty Shared Coherency enabled*/ 298 #define CONFIG_BE 0x00008000 /* Endian-ness: 1 --> BE */ 299 #define CONFIG_EM 0x00004000 /* 1 -> ECC mode, 0 -> parity */ 300 #define CONFIG_EB 0x00002000 /* Block order:1->sequent,0->subblock */ 301 302 #define CONFIG_IC 0x00000e00 /* Primary Icache size */ 303 #define CONFIG_DC 0x000001c0 /* Primary Dcache size */ 304 #define CONFIG_IB 0x00000020 /* Icache block size */ 305 #define CONFIG_DB 0x00000010 /* Dcache block size */ 306 #define CONFIG_CU 0x00000008 /* Update on Store-conditional */ 307 #define CONFIG_K0 0x00000007 /* K0SEG Coherency algorithm */ 308 309 #define CONFIG_UNCACHED 0x00000002 /* K0 is uncached */ 310 #define CONFIG_NONCOHRNT 0x00000003 311 #define CONFIG_COHRNT_EXLWR 0x00000005 312 #define CONFIG_SB_SHFT 22 /* shift SB to bit position 0 */ 313 #define CONFIG_IC_SHFT 9 /* shift IC to bit position 0 */ 314 #define CONFIG_DC_SHFT 6 /* shift DC to bit position 0 */ 315 #define CONFIG_BE_SHFT 15 /* shift BE to bit position 0 */ 316 317 /* 318 * C0_TAGLO definitions for setting/getting cache states and physaddr bits 319 */ 320 #define SADDRMASK 0xFFFFE000 /* 31..13 -> scache paddr bits 35..17 */ 321 #define SVINDEXMASK 0x00000380 /* 9..7: prim virt index bits 14..12 */ 322 #define SSTATEMASK 0x00001c00 /* bits 12..10 hold scache line state */ 323 #define SINVALID 0x00000000 /* invalid --> 000 == state 0 */ 324 #define SCLEANEXCL 0x00001000 /* clean exclusive --> 100 == state 4 */ 325 #define SDIRTYEXCL 0x00001400 /* dirty exclusive --> 101 == state 5 */ 326 #define SECC_MASK 0x0000007f /* low 7 bits are ecc for the tag */ 327 #define SADDR_SHIFT 4 /* shift STagLo (31..13) to 35..17 */ 328 329 #define PADDRMASK 0xFFFFFF00 /* PTagLo31..8->prim paddr bits35..12 */ 330 #define PADDR_SHIFT 4 /* roll bits 35..12 down to 31..8 */ 331 #define PSTATEMASK 0x00C0 /* bits 7..6 hold primary line state */ 332 #define PINVALID 0x0000 /* invalid --> 000 == state 0 */ 333 #define PCLEANEXCL 0x0080 /* clean exclusive --> 10 == state 2 */ 334 #define PDIRTYEXCL 0x00C0 /* dirty exclusive --> 11 == state 3 */ 335 #define PPARITY_MASK 0x0001 /* low bit is parity bit (even). */ 336 337 /* 338 * C0_CACHE_ERR definitions. 339 */ 340 #define CACHERR_ER 0x80000000 /* 0: inst ref, 1: data ref */ 341 #define CACHERR_EC 0x40000000 /* 0: primary, 1: secondary */ 342 #define CACHERR_ED 0x20000000 /* 1: data error */ 343 #define CACHERR_ET 0x10000000 /* 1: tag error */ 344 #define CACHERR_ES 0x08000000 /* 1: external ref, e.g. snoop*/ 345 #define CACHERR_EE 0x04000000 /* error on SysAD bus */ 346 #define CACHERR_EB 0x02000000 /* complicated, see spec. */ 347 #define CACHERR_EI 0x01000000 /* complicated, see spec. */ 348 #define CACHERR_SIDX_MASK 0x003ffff8 /* secondary cache index */ 349 #define CACHERR_PIDX_MASK 0x00000007 /* primary cache index */ 350 #define CACHERR_PIDX_SHIFT 12 /* bits 2..0 are paddr14..12 */ 351 352 /* R4000 family supports hardware watchpoints: 353 * C0_WATCHLO: 354 * bits 31..3 are bits 31..3 of physaddr to watch 355 * bit 2: reserved; must be written as 0. 356 * bit 1: when set causes a watchpoint trap on load accesses to paddr. 357 * bit 0: when set traps on stores to paddr; 358 * C0_WATCHHI 359 * bits 31..4 are reserved and must be written as zeros. 360 * bits 3..0 are bits 35..32 of the physaddr to watch 361 */ 362 #define WATCHLO_WTRAP 0x00000001 363 #define WATCHLO_RTRAP 0x00000002 364 #define WATCHLO_ADDRMASK 0xfffffff8 365 #define WATCHLO_VALIDMASK 0xfffffffb 366 #define WATCHHI_VALIDMASK 0x0000000f 367 368 /* 369 * Coprocessor 0 registers 370 */ 371 #ifdef _LANGUAGE_ASSEMBLY 372 #define C0_INX $0 373 #define C0_RAND $1 374 #define C0_ENTRYLO0 $2 375 #define C0_ENTRYLO1 $3 376 #define C0_CONTEXT $4 377 #define C0_PAGEMASK $5 /* page mask */ 378 #define C0_WIRED $6 /* # wired entries in tlb */ 379 #define C0_BADVADDR $8 380 #define C0_COUNT $9 /* free-running counter */ 381 #define C0_ENTRYHI $10 382 #define C0_SR $12 383 #define C0_CAUSE $13 384 #define C0_EPC $14 385 #define C0_PRID $15 /* revision identifier */ 386 #define C0_COMPARE $11 /* counter comparison reg. */ 387 #define C0_CONFIG $16 /* hardware configuration */ 388 #define C0_LLADDR $17 /* load linked address */ 389 #define C0_WATCHLO $18 /* watchpoint */ 390 #define C0_WATCHHI $19 /* watchpoint */ 391 #define C0_ECC $26 /* S-cache ECC and primary parity */ 392 #define C0_CACHE_ERR $27 /* cache error status */ 393 #define C0_TAGLO $28 /* cache operations */ 394 #define C0_TAGHI $29 /* cache operations */ 395 #define C0_ERROR_EPC $30 /* ECC error prg. counter */ 396 397 # else /* ! _LANGUAGE_ASSEMBLY */ 398 399 #define C0_INX 0 400 #define C0_RAND 1 401 #define C0_ENTRYLO0 2 402 #define C0_ENTRYLO1 3 403 #define C0_CONTEXT 4 404 #define C0_PAGEMASK 5 /* page mask */ 405 #define C0_WIRED 6 /* # wired entries in tlb */ 406 #define C0_BADVADDR 8 407 #define C0_COUNT 9 /* free-running counter */ 408 #define C0_ENTRYHI 10 409 #define C0_SR 12 410 #define C0_CAUSE 13 411 #define C0_EPC 14 412 #define C0_PRID 15 /* revision identifier */ 413 #define C0_COMPARE 11 /* counter comparison reg. */ 414 #define C0_CONFIG 16 /* hardware configuration */ 415 #define C0_LLADDR 17 /* load linked address */ 416 #define C0_WATCHLO 18 /* watchpoint */ 417 #define C0_WATCHHI 19 /* watchpoint */ 418 #define C0_ECC 26 /* S-cache ECC and primary parity */ 419 #define C0_CACHE_ERR 27 /* cache error status */ 420 #define C0_TAGLO 28 /* cache operations */ 421 #define C0_TAGHI 29 /* cache operations */ 422 #define C0_ERROR_EPC 30 /* ECC error prg. counter */ 423 424 #endif /* _LANGUAGE_ASSEMBLY */ 425 426 /* 427 * floating-point status register 428 */ 429 #define FPCSR_FS 0x01000000 /* flush denorm to zero */ 430 #define FPCSR_C 0x00800000 /* condition bit */ 431 #define FPCSR_CE 0x00020000 /* cause: unimplemented operation */ 432 #define FPCSR_CV 0x00010000 /* cause: invalid operation */ 433 #define FPCSR_CZ 0x00008000 /* cause: division by zero */ 434 #define FPCSR_CO 0x00004000 /* cause: overflow */ 435 #define FPCSR_CU 0x00002000 /* cause: underflow */ 436 #define FPCSR_CI 0x00001000 /* cause: inexact operation */ 437 #define FPCSR_EV 0x00000800 /* enable: invalid operation */ 438 #define FPCSR_EZ 0x00000400 /* enable: division by zero */ 439 #define FPCSR_EO 0x00000200 /* enable: overflow */ 440 #define FPCSR_EU 0x00000100 /* enable: underflow */ 441 #define FPCSR_EI 0x00000080 /* enable: inexact operation */ 442 #define FPCSR_FV 0x00000040 /* flag: invalid operation */ 443 #define FPCSR_FZ 0x00000020 /* flag: division by zero */ 444 #define FPCSR_FO 0x00000010 /* flag: overflow */ 445 #define FPCSR_FU 0x00000008 /* flag: underflow */ 446 #define FPCSR_FI 0x00000004 /* flag: inexact operation */ 447 #define FPCSR_RM_MASK 0x00000003 /* rounding mode mask */ 448 #define FPCSR_RM_RN 0x00000000 /* round to nearest */ 449 #define FPCSR_RM_RZ 0x00000001 /* round to zero */ 450 #define FPCSR_RM_RP 0x00000002 /* round to positive infinity */ 451 #define FPCSR_RM_RM 0x00000003 /* round to negative infinity */ 452 453 #endif /* __R4300_H */